#ifndef __VPSS_HAL_IP_MMU_H__
#define __VPSS_HAL_IP_MMU_H__

#include "hi_reg_common.h"
#include "vpss_define.h"


HI_VOID VPSS_MMU_SetPtwPf                 ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptw_pf                    );
HI_VOID VPSS_MMU_SetIntEn                 ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 int_en                    );
HI_VOID VPSS_MMU_SetGlbBypass             ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 glb_bypass                );
HI_VOID VPSS_MMU_SetSmmuIdle              ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 smmu_idle                 );
HI_VOID VPSS_MMU_SetAutoClkGtEn           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 auto_clk_gt_en            );
HI_VOID VPSS_MMU_SetRfsRet1n              ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 rfs_ret1n                 );
HI_VOID VPSS_MMU_SetRfsEma                ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 rfs_ema                   );
HI_VOID VPSS_MMU_SetRfsEmaw               ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 rfs_emaw                  );
HI_VOID VPSS_MMU_SetIntsTlbinvalidWrMsk   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbinvalid_wr_msk    );
HI_VOID VPSS_MMU_SetIntsTlbinvalidRdMsk   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbinvalid_rd_msk    );
HI_VOID VPSS_MMU_SetIntsPtwTransMsk       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_ptw_trans_msk        );
HI_VOID VPSS_MMU_SetIntsTlbmissMsk        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbmiss_msk          );
HI_VOID VPSS_MMU_SetIntsTlbinvalidWrRaw   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbinvalid_wr_raw    );
HI_VOID VPSS_MMU_SetIntsTlbinvalidRdRaw   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbinvalid_rd_raw    );
HI_VOID VPSS_MMU_SetIntsPtwTransRaw       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_ptw_trans_raw        );
HI_VOID VPSS_MMU_SetIntsTlbmissRaw        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbmiss_raw          );
HI_VOID VPSS_MMU_SetIntsTlbinvalidWrStat  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbinvalid_wr_stat   );
HI_VOID VPSS_MMU_SetIntsTlbinvalidRdStat  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbinvalid_rd_stat   );
HI_VOID VPSS_MMU_SetIntsPtwTransStat      ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_ptw_trans_stat       );
HI_VOID VPSS_MMU_SetIntsTlbmissStat       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbmiss_stat         );
HI_VOID VPSS_MMU_SetIntsTlbinvalidWrClr   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbinvalid_wr_clr    );
HI_VOID VPSS_MMU_SetIntsTlbinvalidRdClr   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbinvalid_rd_clr    );
HI_VOID VPSS_MMU_SetIntsPtwTransClr       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_ptw_trans_clr        );
HI_VOID VPSS_MMU_SetIntsTlbmissClr        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ints_tlbmiss_clr          );
HI_VOID VPSS_MMU_SetIntnsTlbinvalidWrMsk  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbinvalid_wr_msk   );
HI_VOID VPSS_MMU_SetIntnsTlbinvalidRdMsk  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbinvalid_rd_msk   );
HI_VOID VPSS_MMU_SetIntnsPtwTransMsk      ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_ptw_trans_msk       );
HI_VOID VPSS_MMU_SetIntnsTlbmissMsk       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbmiss_msk         );
HI_VOID VPSS_MMU_SetIntnsTlbinvalidWrRaw  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbinvalid_wr_raw   );
HI_VOID VPSS_MMU_SetIntnsTlbinvalidRdRaw  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbinvalid_rd_raw   );
HI_VOID VPSS_MMU_SetIntnsPtwTransRaw      ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_ptw_trans_raw       );
HI_VOID VPSS_MMU_SetIntnsTlbmissRaw       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbmiss_raw         );
HI_VOID VPSS_MMU_SetIntnsTlbinvalidWrStat ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbinvalid_wr_stat  );
HI_VOID VPSS_MMU_SetIntnsTlbinvalidRdStat ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbinvalid_rd_stat  );
HI_VOID VPSS_MMU_SetIntnsPtwTransStat     ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_ptw_trans_stat      );
HI_VOID VPSS_MMU_SetIntnsTlbmissStat      ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbmiss_stat        );
HI_VOID VPSS_MMU_SetIntnsTlbinvalidWrClr  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbinvalid_wr_clr   );
HI_VOID VPSS_MMU_SetIntnsTlbinvalidRdClr  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbinvalid_rd_clr   );
HI_VOID VPSS_MMU_SetIntnsPtwTransClr      ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_ptw_trans_clr       );
HI_VOID VPSS_MMU_SetIntnsTlbmissClr       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 intns_tlbmiss_clr         );
HI_VOID VPSS_MMU_SetScbTtbrH              ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 scb_ttbr_h                );
HI_VOID VPSS_MMU_SetScbTtbr               ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 scb_ttbr                  );
HI_VOID VPSS_MMU_SetCbTtbrH               ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cb_ttbr_h                 );
HI_VOID VPSS_MMU_SetCbTtbr                ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cb_ttbr                   );
HI_VOID VPSS_MMU_SetErrSRdAddrH           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 err_s_rd_addr_h           );
HI_VOID VPSS_MMU_SetErrSRdAddr            ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 err_s_rd_addr             );
HI_VOID VPSS_MMU_SetErrSWrAddrH           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 err_s_wr_addr_h           );
HI_VOID VPSS_MMU_SetErrSWrAddr            ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 err_s_wr_addr             );
HI_VOID VPSS_MMU_SetErrNsRdAddrH          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 err_ns_rd_addr_h          );
HI_VOID VPSS_MMU_SetErrNsRdAddr           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 err_ns_rd_addr            );
HI_VOID VPSS_MMU_SetErrNsWrAddrH          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 err_ns_wr_addr_h          );
HI_VOID VPSS_MMU_SetErrNsWrAddr           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 err_ns_wr_addr            );
HI_VOID VPSS_MMU_SetFaultAddrhPtwS        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_addrh_ptw_s         );
HI_VOID VPSS_MMU_SetFaultAddrPtwS         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_addr_ptw_s          );
HI_VOID VPSS_MMU_SetFaultStrmIdS          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_strm_id_s           );
HI_VOID VPSS_MMU_SetFaultIndexIdS         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_index_id_s          );
HI_VOID VPSS_MMU_SetFaultAddrhPtwNs       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_addrh_ptw_ns        );
HI_VOID VPSS_MMU_SetFaultAddrPtwNs        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_addr_ptw_ns         );
HI_VOID VPSS_MMU_SetFaultStrmIdNs         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_strm_id_ns          );
HI_VOID VPSS_MMU_SetFaultIndexIdNs        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_index_id_ns         );
HI_VOID VPSS_MMU_SetFaultNsPtwNum         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_ns_ptw_num          );
HI_VOID VPSS_MMU_SetFaultSPtwNum          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_s_ptw_num           );
HI_VOID VPSS_MMU_SetFaultAddrWrS          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_addr_wr_s           );
HI_VOID VPSS_MMU_SetFaultTlbWrS           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tlb_wr_s            );
HI_VOID VPSS_MMU_SetFaultStrIdWrS         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_str_id_wr_s         );
HI_VOID VPSS_MMU_SetFaultIndexIdWrS       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_index_id_wr_s       );
HI_VOID VPSS_MMU_SetFaultAddrWrNs         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_addr_wr_ns          );
HI_VOID VPSS_MMU_SetFaultTlbWrNs          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tlb_wr_ns           );
HI_VOID VPSS_MMU_SetFaultStrIdWrNs        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_str_id_wr_ns        );
HI_VOID VPSS_MMU_SetFaultIndexIdWrNs      ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_index_id_wr_ns      );
HI_VOID VPSS_MMU_SetFaultAddrRdS          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_addr_rd_s           );
HI_VOID VPSS_MMU_SetFaultTlbRdS           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tlb_rd_s            );
HI_VOID VPSS_MMU_SetFaultStrIdRdS         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_str_id_rd_s         );
HI_VOID VPSS_MMU_SetFaultIndexIdRdS       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_index_id_rd_s       );
HI_VOID VPSS_MMU_SetFaultAddrRdNs         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_addr_rd_ns          );
HI_VOID VPSS_MMU_SetFaultTlbRdNs          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tlb_rd_ns           );
HI_VOID VPSS_MMU_SetFaultStrIdRdNs        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_str_id_rd_ns        );
HI_VOID VPSS_MMU_SetFaultIndexIdRdNs      ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_index_id_rd_ns      );
HI_VOID VPSS_MMU_SetFaultTbuNum           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tbu_num             );
HI_VOID VPSS_MMU_SetFaultTlbinvalidErrNs  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tlbinvalid_err_ns   );
HI_VOID VPSS_MMU_SetFaultTlbmissErrNs     ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tlbmiss_err_ns      );
HI_VOID VPSS_MMU_SetFaultTlbinvalidErrS   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tlbinvalid_err_s    );
HI_VOID VPSS_MMU_SetFaultTlbmissErrS      ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 fault_tlbmiss_err_s       );
HI_VOID VPSS_MMU_SetReadCommandCounter    ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 read_command_counter      );
HI_VOID VPSS_MMU_SetArchStallN            ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 arch_stall_n              );
HI_VOID VPSS_MMU_SetTbuArreadym           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 tbu_arreadym              );
HI_VOID VPSS_MMU_SetArReadys              ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ar_readys                 );
HI_VOID VPSS_MMU_SetArValids              ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ar_valids                 );
HI_VOID VPSS_MMU_SetWriteCommandCounter   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 write_command_counter     );
HI_VOID VPSS_MMU_SetAwchStallN            ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 awch_stall_n              );
HI_VOID VPSS_MMU_SetTbuAwreadym           ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 tbu_awreadym              );
HI_VOID VPSS_MMU_SetAwReadys              ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 aw_readys                 );
HI_VOID VPSS_MMU_SetAwValids              ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 aw_valids                 );
HI_VOID VPSS_MMU_SetPrefBufferEmpty       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 pref_buffer_empty         );
HI_VOID VPSS_MMU_SetPtwq15IdleState       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq15_idle_state         );
HI_VOID VPSS_MMU_SetPtwq14IdleState       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq14_idle_state         );
HI_VOID VPSS_MMU_SetPtwq13IdleState       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq13_idle_state         );
HI_VOID VPSS_MMU_SetPtwq12IdleState       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq12_idle_state         );
HI_VOID VPSS_MMU_SetPtwq11IdleState       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq11_idle_state         );
HI_VOID VPSS_MMU_SetPtwq10IdleState       ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq10_idle_state         );
HI_VOID VPSS_MMU_SetPtwq9IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq9_idle_state          );
HI_VOID VPSS_MMU_SetPtwq8IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq8_idle_state          );
HI_VOID VPSS_MMU_SetPtwq7IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq7_idle_state          );
HI_VOID VPSS_MMU_SetPtwq6IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq6_idle_state          );
HI_VOID VPSS_MMU_SetPtwq5IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq5_idle_state          );
HI_VOID VPSS_MMU_SetPtwq4IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq4_idle_state          );
HI_VOID VPSS_MMU_SetPtwq3IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq3_idle_state          );
HI_VOID VPSS_MMU_SetPtwq2IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq2_idle_state          );
HI_VOID VPSS_MMU_SetPtwq1IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq1_idle_state          );
HI_VOID VPSS_MMU_SetPtwq0IdleState        ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 ptwq0_idle_state          );
HI_VOID VPSS_MMU_SetSmmuRstState          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 smmu_rst_state            );
HI_VOID VPSS_MMU_SetInOutCmdCntRd         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 in_out_cmd_cnt_rd         );
HI_VOID VPSS_MMU_SetRdyDebugRd            ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 rdy_debug_rd              );
HI_VOID VPSS_MMU_SetVldDebugRd            ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 vld_debug_rd              );
HI_VOID VPSS_MMU_SetCurMissCntRd          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_miss_cnt_rd           );
HI_VOID VPSS_MMU_SetLastMissCntRd         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_miss_cnt_rd          );
HI_VOID VPSS_MMU_SetInOutCmdCntWr         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 in_out_cmd_cnt_wr         );
HI_VOID VPSS_MMU_SetRdyDebugWr            ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 rdy_debug_wr              );
HI_VOID VPSS_MMU_SetVldDebugWr            ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 vld_debug_wr              );
HI_VOID VPSS_MMU_SetCurMissCntWr          ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_miss_cnt_wr           );
HI_VOID VPSS_MMU_SetLastMissCntWr         ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_miss_cnt_wr          );
HI_VOID VPSS_MMU_SetCurDoubleUpdCntRd     ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_double_upd_cnt_rd     );
HI_VOID VPSS_MMU_SetLastDoubleUpdCntRd    ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_double_upd_cnt_rd    );
HI_VOID VPSS_MMU_SetCurDoubleMissCntRd    ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_double_miss_cnt_rd    );
HI_VOID VPSS_MMU_SetLastDoubleMissCntRd   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_double_miss_cnt_rd   );
HI_VOID VPSS_MMU_SetMstFsmCur             ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 mst_fsm_cur               );
HI_VOID VPSS_MMU_SetCurDoubleUpdCntWr     ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_double_upd_cnt_wr     );
HI_VOID VPSS_MMU_SetLastDoubleUpdCntWr    ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_double_upd_cnt_wr    );
HI_VOID VPSS_MMU_SetCurDoubleMissCntWr    ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_double_miss_cnt_wr    );
HI_VOID VPSS_MMU_SetLastDoubleMissCntWr   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_double_miss_cnt_wr   );
HI_VOID VPSS_MMU_SetLastSel1ChnMissCntRd  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_sel1_chn_miss_cnt_rd );
HI_VOID VPSS_MMU_SetCurSel1ChnMissCntRd   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_sel1_chn_miss_cnt_rd  );
HI_VOID VPSS_MMU_SetLastSel2ChnMissCntRd  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_sel2_chn_miss_cnt_rd );
HI_VOID VPSS_MMU_SetCurSel2ChnMissCntRd   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_sel2_chn_miss_cnt_rd  );
HI_VOID VPSS_MMU_SetLastSel1ChnMissCntWr  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_sel1_chn_miss_cnt_wr );
HI_VOID VPSS_MMU_SetCurSel1ChnMissCntWr   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_sel1_chn_miss_cnt_wr  );
HI_VOID VPSS_MMU_SetLastSel2ChnMissCntWr  ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 last_sel2_chn_miss_cnt_wr );
HI_VOID VPSS_MMU_SetCurSel2ChnMissCntWr   ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 cur_sel2_chn_miss_cnt_wr  );
HI_VOID VPSS_MMU_SetSel1ChnRd             ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 sel1_chn_rd               );
HI_VOID VPSS_MMU_SetSel2ChnRd             ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 sel2_chn_rd               );
HI_VOID VPSS_MMU_SetSel1ChnWr             ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 sel1_chn_wr               );
HI_VOID VPSS_MMU_SetSel2ChnWr             ( S_VPSS_REGS_TYPE *pstReg, HI_U32 offset, HI_U32 sel2_chn_wr               );

HI_U32 VPSS_MMU_GetIntsStat(S_VPSS_REGS_TYPE *pVpssReg, HI_U32 layer);
HI_VOID VPSS_MMU_SetIntsClr(S_VPSS_REGS_TYPE *pVpssReg, HI_U32 layer, HI_U32 ints_clr);
HI_U32 VPSS_MMU_GetIntnsStat(S_VPSS_REGS_TYPE *pVpssReg, HI_U32 layer);
HI_VOID VPSS_MMU_SetIntnsClr(S_VPSS_REGS_TYPE *pVpssReg, HI_U32 layer, HI_U32 intns_clr);

#endif

